Department of Electrical Engineering organizing
Five Day Workshop on:

October 02 - 06, 2020 
Supported by TEQIP-III (NPIU, MHRD, Government of India)

Course Contents:

1. Circuit elements in a CMOS process- Components available in CMOS process; resistors, transistors, capacitors and their layouts.
2. Basic amplifier design- Various amplifier topologies S, CG, CD; signal coupling and biasing.
3. Mismatch and noise- Mismatch in a CMOS process; noise in electrical circuits.
4. Operational amplifier design and layout- Single stage and two stage opamp design; layout of an opamp.
Software tools to be used- LTspice simulator, Magic VLSI layout editor

 Intended Participants:

The workshop is intended for TEQIP Faculty  


There are two pages in the form for you to fill up. After submitting the form, you will receive a mail from with an attachment of the filled form by the end of the day. You need to take a print of this form and write your institution full name if it is not there in the list and get it signed digitally by your institution's TEQIP coordinator/director, and send its scanned copy to You will receive a mail if your participation is confirmed. Please note that participation is allotted on a first come first serve basis.

Registrations Closed



Dr. Abhishek Kumar

Important Dates

Workshop Date: October 02 - 06, 2020

Last date for Online registration is 29th September, 2020 and receiving the scanned copy of the digitally signed registration form is 29th September, 2020. Participation will be allotted strictly on a first come first serve basis
Note: Confirmation mail will be sent on 01 st October, 2020.

Last Modified: October 1, 2020 at 4:43 pm